module ram_scanner(
    input  sys_rst_n,
    input  sys_clk,
    input  pll_clk,
    // Dual DA
    output dac0_clk,
    output dac1_clk,
    output [7:0] dac0_data,
    output [7:0] dac1_data,
    // FT232H
    input usb_clk_60m,
    input usb_rxf_n,
    input [7:0] usb_data,
    // rom
    output [10:0] bram_rd_addr,
    input [7:0] bram_rd_data
);

/**********计时部分**********/
parameter count_value       = 13_500_000;

reg [23:0]  count_value_reg ;

always @(posedge sys_clk) begin
    if (!sys_rst_n) 
        begin
            count_value_reg  <= 23'b0;
        end 
    else
        begin 
            if (count_value_reg <= count_value) begin
                count_value_reg  <= count_value_reg + 1'b1;
            end else begin
                count_value_reg  <= 23'b0;
            end
        end
end

reg [10:0] bram_rd_addr_reg = 11'b0;
reg [7:0] da0_data_pulse = 8'b0;
reg [7:0] da1_data_pulse = 8'b0;

always @(negedge pll_clk) begin
    if (bram_rd_addr_reg[0] == 1'b1)
        da0_data_pulse <= bram_rd_data;
    else
        da1_data_pulse <= bram_rd_data;
end

reg [7:0] da1_data;

assign dac0_clk = ~pll_clk;
assign dac0_data = da0_data_pulse;
assign dac1_clk = ~pll_clk;
assign dac1_data = da1_data_pulse;

wire dac_sys_clk_dbg;
assign dac_sys_clk_dbg = sys_clk;
assign bram_rd_addr = bram_rd_addr_reg;

always @(posedge pll_clk or negedge sys_rst_n) begin
    if (!sys_rst_n)
        bram_rd_addr_reg <= 5'b0;
    else if (bram_rd_addr_reg < 11'd512) // 245FIFO tranfers 512 Bytes Once and have to restart
        bram_rd_addr_reg <= bram_rd_addr_reg + 5'b1;
    else
        bram_rd_addr_reg <= 5'b0;
end

endmodule